//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
//Date        : Wed Apr 30 20:28:21 2025
//Host        : LAPTOP-EUGMKLPQ running 64-bit major release  (build 9200)
//Command     : generate_target system_wrapper.bd
//Design      : system_wrapper
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module system_wrapper
   (LED,
    clk,
    rstn,
    uart_rxd,
    uart_txd);
  output [1:0]LED;
  input clk;
  input rstn;
  input uart_rxd;
  output uart_txd;

  wire [1:0]LED;
  wire clk;
  wire rstn;
  wire uart_rxd;
  wire uart_txd;

  system system_i
       (.LED(LED),
        .clk(clk),
        .rstn(rstn),
        .uart_rxd(uart_rxd),
        .uart_txd(uart_txd));
endmodule
